FPGA Piano
Demo
Overview
The BAYSE-3 Piano was developed as the final project for CS 233: Computer Architecture (Honors) at UIUC. The project demonstrates a complete audio synthesis pipeline built directly on an FPGA, converting switch and button inputs into real-time musical tones using digital waveform generation and DAC-based analog output.
The piano implements multiple octaves, volume modes, and chord support, with all sound generation handled purely in hardware using Verilog. The project highlights proficiency in digital design, modular synthesis, and signal path control through HDL.
Hardware
Implemented on the BAYSE-3 FPGA board (Digilent BASYS3, Xilinx Artix-7), utilizing the PMOD R2R DAC for audio output and an external op-amp amplifier to drive a speaker. Input controls via onboard switches and buttons.
- Platform: Digilent BASYS3 FPGA board (Xilinx Artix-7).
- DAC Output: Pmod R2R resistor ladder on the JG port.
- Amplification: SparkFun Audio Amplifier to drive speaker output.
- Speaker: Mini 0.5W Speaker for analog sound output.
Logic Design
- Pure hardware implementation in Verilog — no software processor used.
- Each piano key generates a programmable frequency tone through a digital divider circuit.
- Octave control implemented via frequency scaling logic triggered by BTNL/BTNR inputs.
- Supports simultaneous key presses for chord generation using summed digital signals.
- Volume toggling implemented through high/low bit scaling using SW0.
Results
The BAYSE-3 Piano successfully produced clear, stable musical tones across multiple octaves. The system detected multiple simultaneous key presses for full chord generation. Frequency transitions between octaves were smooth, and DAC output was clean after amplification. The final demo demonstrated robust and responsive sound generation fully in hardware.
Future Work
- Add on-board display to visualize selected note and octave.
- Expand to include MIDI-over-USB support for external keyboard control.
- Implement smoother chord transitions.
Code / Report
Complete Verilog source code, design files, and build instructions available on GitHub. All modules built and tested in Vivado.