Chess Arcade

The AI Chess Arcade Game was developed as the final project for ECE 385: Digital Systems Laboratory at UIUC. The goal was to design a hardware-based chess system integrating FPGA logic, embedded software, and an AI opponent into a single interactive arcade-style platform.

The project demonstrates skills across hardware design, SystemVerilog programming, low-level C embedded programming, and application of AI on top of a SoC platform. The player interacts using a physical USB mouse while the FPGA renders the board (custom graphics driver) and manages gameplay logic (custom C chess engine, minimal memory usage) in real time.

The design was implemented on a prebuilt FPGA development board used in ECE 385. Peripherals including VGA output, USB mouse input, and on-board switches were connected via jumper wiring.

• Designed SystemVerilog modules for a graphics driver with frame buffering using AXI BRAM storage.
• Integrated USB mouse input through a custom SPI interface driver.

• Software runs on a MicroBlaze SoC with BRAM and a custom AXI driver for SPI, graphics control, and custom GPIO.
• Game logic optimized to be queried by Minimax.
• Implements Minimax algorithm with alpha-beta pruning for efficient search.
• USB host and graphics rendering synchronized through shared memory-mapped registers connecting to SystemVerilog code on the FPGA.

System emulates a full chess game with an interface enabling the Minimax algorithm to quickly evaluate board states. Custom graphics driver with Python graphics encoding script enabled downloading images from the internet for use as sprites. Frame buffer enabled smooth mouse movement. SPI interface with USB-HID driver using public library (lw_usb) enabled quick mouse control. The final demonstration achieved bug-free gameplay across all game modes.

• Port to a different FPGA board with proper hardware setup.
• Add DDR3 memory interface for better AI performance.
• Train a heuristic model for improved AI evaluation.
• Add sound output and score tracking through peripheral expansion.

Complete documentation including design methodology, test results, and code structure.